In a high-speed serial circuit, where should the DC blocking capacitor be placed? Some engineers simply say it should be placed on either the driver or the receiver. Others argue that it's better to place it on the receiving end. Their reasoning is that as the signal travels from the driver to the receiver through the transmission line, it experiences attenuation and increased rise time. By the time it reaches the capacitor at the receiver, most of the high-frequency components have already been lost, which reduces reflections and allows more of the signal to reach the receiver.
An SI engineer might explain that for all passive elements in the system, each component influences the others, and the entire topology is interconnected regardless of the signal direction. Therefore, the position of the capacitor doesn’t matter much from a frequency domain perspective.
To resolve this, we can analyze the problem using both time-domain and frequency-domain approaches. Let’s take a simple topology that includes a short transmission line, a long transmission line, several vias, and a capacitor placed near one end, as shown in Figure 1.
Figure 1: Schematic diagram of a simple topology (DC blocking capacitor is close to the receiving end)
Creating detailed models for such topologies requires significant effort. In this case, we simplify things by using a lumped model to illustrate the concept. The theory remains consistent with that of a more complex model.
Figure 2 shows the RLGC parameters for a uniform, passive, and causal transmission line with a characteristic impedance of 50Ω, a loss angle of 0.0016, a linewidth of 3 mils, a DK of 3.9, and a propagation delay of approximately 173 ps/inch at 1 GHz.
Figure 2: Transmission line impedance (left); transmission line delay (right)
The via is modeled as a simple 2 pF shunt capacitor, as shown in Figure 3.
Figure 3: Parallel capacitor
Finally, the capacitor model includes a series RL to represent internal parasitic parameters, with a shunt capacitor at each end connected to the transmission line to simulate pads and vias, as shown in Figure 4.
Figure 4: Capacitor model
For the capacitive model, the main series capacitor is removed to allow for a DC path and further TDR signal analysis. Although this may seem unusual, most high-speed signal protocols below 100 MHz are DC balanced. Above these frequencies, the model of adding a series capacitor or short-circuiting at an appropriate location looks similar to Figure 4, and it’s necessary to include parasitic inductance and current-limiting capacitance at the frequencies of interest.
Once all the models are built, they are connected in series. To answer the initial question, we consider two scenarios:
a. Port-1 is the driver, and Port-2 is the receiver (capacitor is close to the receiver)
b. Port-2 is the driver, and Port-1 is the receiver (capacitor is close to the driver)
By inputting a pulse into Port-1 and observing the response at Port-2, and then reversing the process (inputting a signal into Port-2 and observing the response at Port-1), we can determine whether the placement of the capacitor makes a difference.
Figure 5: Time domain pulse (left); forward and backward loss (right)
The results in Figure 5 show that the waveforms are almost indistinguishable, indicating that the position of the capacitor has no significant effect on the signal in this particular topology and configuration.
However, looking at the S-parameters (for a two-port passive network, S21 = S12), we find that the frequency domain view is correct, while the time domain view was misleading in this case.
Figure 6: TDR curve (ports 1 and 2); return loss (S11 and S22)
Now, let’s explore another scenario. We create a topology with a total length of 11 inches and move the capacitors from one end to the center in different increments. Theoretically, we shouldn’t see any differences.
Figure 7: Rise time observed at the receiving end (left); entire pulse waveform, magnified reflection (right)
From Figure 7, we observe an interesting phenomenon: when the capacitor moves from the driver end to the middle of the transmission line, the signal at the receiving end changes, proving that the capacitor's position affects the signal. However, once the position is fixed, the signal is the same regardless of whether the driver is on the left or the right.
When the capacitor is moved toward the ends, we can observe reflections at different times between the two ends. When the DC blocking capacitors are placed at both ends, most of the bandwidth is concentrated on the rising edge.
Figure 8: 1/2 harmonic of each type of length
From Figure 8, we can estimate the position of the DC blocking capacitor based on the resonance points. The calculated distance to one end is approximately 1 inch, and to the other end is about 3 inches, which matches our expectations.
These discontinuous pulses continue to reflect back and forth until the natural losses of the transmission line attenuate them. These reflections interfere with subsequent parts of the signal, ultimately reducing the quality of the eye diagram at the receiving end.
What happens if there are more losses on the transmission line? Let’s test that.
Figure 9: Resonance of each dielectric loss (left); loss (right)
As shown in Figure 9, increasing the dielectric loss angle reduces the signal strength but also diminishes the resonance peaks. In many cases, additional loss can help attenuate unwanted resonances.
Before testing, we ensure that the source and receiver impedances are matched to 50 Ohms, matching the transmission line. What happens if the capacitor is placed on the driver side and the source impedance changes from 40 Ohms to 50 Ohms?
Figure 10: Results of 40 ohm and 50 ohm source impedance
As seen in Figure 10, changing the source impedance affects the steady-state voltage, but the size of the discontinuity point remains largely unchanged. The amplitude of the signal isn't significantly affected, but the difference between the transmission line discontinuity and the discontinuities at both ends does affect the amplitude of the 1/2 harmonic.
In this example, the source impedance ranges from 40 to 55 Ohms, and although the high level of the pulse changes as expected, the overall waveform remains largely unaffected.
Looking at the differential impedances of the capacitor at two different positions, as shown in Figure 11, we see that the main factors affecting these points are the capacitance itself, not the drive impedance.
Figure 11: Add a capacitor at 0.1 inch at the source (left); add a capacitor at 3 inch at the source (left)
If we remove all capacitors, the simulation topology becomes symmetrical, with the same number of discontinuities at both ends. But what if the topology is not uniform? For example, if there is a connector near one end, how would that affect the result?
To test this, we double the via at one end and run two examples simultaneously. In the first case, the DC blocking capacitor is 10 inches away from the via, and in the second case, it's only 1 inch away.
Figure 12: Step response (left); loss (right)
As shown in Figure 12, the results differ in both time and frequency domains. When the capacitor is closer to the via, the reflection is relatively larger. However, it's not always the best choice to place the capacitor on the side with the largest discontinuity. It depends on the specific topology, the type of discontinuity, and how you use these discontinuities to place the capacitor.
The key takeaway is to place the capacitor in a way that minimizes the discontinuity of the transmission line. A smaller discontinuity means less reflection.
From an SI perspective, we can conclude:
1. The capacitor should be placed to minimize the discontinuity of the transmission line. The smaller the discontinuity, the less reflection it produces.
2. The overall capacitance should be placed closer to the driver or receiver, ideally within 1/2 of the UI length, to reduce its impact on the eye diagram and avoid reducing the eye margin.
3. Once the capacitor's position is determined, the topology's appearance shouldn't matter. Whether it's the driver or the receiver doesn't make a difference.
Returning to the original question, we can say that both answers are correct. From a time-domain perspective, the capacitor doesn't matter, but from a frequency-domain perspective, its placement does. Ultimately, the goal is to place the capacitor in a way that minimizes reflections and improves signal integrity.
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