In a high-speed serial circuit, the placement of a DC blocking capacitor is often debated. Some engineers suggest placing it on the driver, while others argue for the receiver. But is there a definitive answer?
Some believe that placing the capacitor at the receiving end helps reduce signal distortion. The reasoning is that as the signal travels from the driver to the receiver through the transmission line, it experiences attenuation and increased rise time. By the time it reaches the capacitor, most high-frequency components have been lost, reducing reflections and allowing more signal to reach the receiver.
On the other hand, an SI engineer might explain that in a passive system, all elements interact, and the entire topology matters—regardless of signal direction. So, the capacitor's position may not significantly impact performance in terms of frequency domain analysis.
To explore this, we analyzed the problem using both time-domain and frequency-domain approaches. We considered a simple topology with a short or long transmission line, several vias, and a capacitor placed near one end.
We used a lumped model to simplify the analysis, which mirrors the behavior of a complex model. For example, Figure 1 shows a schematic where the DC blocking capacitor is close to the receiving end.
Figure 2 illustrates the RLGC parameters of a uniform transmission line with a characteristic impedance of 50Ω, a loss angle of 0.0016, and a propagation delay of about 173ps per inch at 1GHz.
The via was modeled as a simple 2pF shunt capacitor (Figure 3), and the capacitor itself was represented as an RL series model, including parasitic elements (Figure 4).
Even though removing the main series capacitor allows for a DC path, many high-speed protocols are DC-balanced below 100MHz. Above that, adding a series capacitor or a short circuit looks similar, but it’s important to include parasitics at the relevant frequencies.
After building the models and connecting them in series, we tested two scenarios: one where Port-1 was the driver and Port-2 the receiver (capacitor near the receiver), and another where Port-2 was the driver and Port-1 the receiver (capacitor near the driver).
In both cases, the pulse response at the receiving end showed no significant difference, suggesting that the capacitor’s position had little effect in this setup.
However, when looking at the return loss (S11 and S22) in Figure 6, the discontinuity at Port-2 (near the capacitor) was much larger than at Port-1. This indicates that the capacitor’s position does affect signal integrity, even if the overall waveform remains similar.
To further test, we moved the capacitor along the transmission line and observed changes in the received signal. When the capacitor was near the center, the signal changed, showing that the location affects the signal. However, once the position was fixed, the signal remained the same regardless of whether the driver was on the left or right.
By analyzing the resonance points in Figure 8, we could estimate the capacitor’s location based on the harmonic peaks. Moving the capacitor closer to the ends introduced different reflection times, and when placed at both ends, it affected the eye diagram by introducing interference.
Adding more losses to the transmission line helped reduce these resonances, as seen in Figure 9. Even with varying source impedances (from 40Ω to 50Ω), the overall waveform remained stable, though the steady-state voltage changed slightly.
From the differential impedance plots in Figure 11, we saw that the capacitance itself had a greater impact than the driving impedance.
Finally, when we introduced asymmetry—like a connector near one end—the results varied depending on the capacitor’s placement. Placing the capacitor closer to the via caused larger reflections, but this wasn’t always the worst choice. It ultimately depends on the specific topology and how discontinuities are managed.
In conclusion, from an SI perspective:
1. The capacitor should be placed to minimize transmission line discontinuities.
2. It should be positioned closer to the driver or receiver, preferably within 1/2 of the UI length, to reduce eye diagram distortion.
3. Once the position is determined, the topology doesn’t matter—whether it’s a driver or receiver.
So, the initial question has a nuanced answer: the capacitor’s placement isn’t critical in some cases, but when considering the full topology, it matters. The key is to place it in a way that reduces reflections and maintains signal integrity.
Door Contact Switch,Contact Switch For Door,Magnetic Door Contact Switch,Normally Open Door Contact
Shanghai Janetec Electric Co., Ltd. , https://www.janetecelectric.com