**Abstract:**
In order to address the issue of high control overhead and low efficiency in coarse-grained cryptographic logic arrays, this paper proposes a four-layer control model based on research into the three-layer control framework commonly used in array processing architectures. A programmable control network is designed and implemented to support the control flow mapping of symmetric algorithms such as AES and A5-1. The design was synthesized using a 65 nm CMOS process, resulting in a total area of 13,712 μm², equivalent to approximately 0.95 million NAND gates, which accounts for 0.37% of the overall array area. The maximum operating frequencies achieved for AES and A5-1 are 1,389 MHz and 1,190 MHz, respectively, making it suitable for small-scale and high-speed applications. A comparative analysis of six performance aspects between the four-layer and three-layer control models shows that the former significantly outperforms the latter, meeting the high-efficiency control demands of various network interconnection structures.
**Introduction**
With the rapid growth of network bandwidth and the increasing diversity of network security protocols, the scope of cryptographic applications has expanded significantly, placing higher demands on the performance of cryptographic devices. For computationally intensive algorithms, the Coarse-Grained Cryptographic Logic Array (CGCLA) architecture leverages data parallelism and pipeline characteristics to enable fast and flexible cryptographic operations. However, if the controller suffers from poor efficiency, excessive delay, or large area consumption, the control path may become a bottleneck, leading to increased costs and reduced scalability. Therefore, an efficient controller is crucial for achieving optimal performance in CGCLA systems.
This paper investigates the control mechanisms of three mainstream reconfigurable cryptographic architectures. It identifies limitations in the ADRES, XPP, and MorphoSys architectures, such as poor scalability, limited control scope, and high interaction overhead. Based on the structural features of symmetric cryptographic algorithms, this study introduces a four-layer control model that incorporates full dynamic configuration technology. The proposed programmable control network addresses issues like poor scalability, long interaction times, and single control flows, effectively supporting both block cipher and stream cipher algorithms.
**1. Research on Control Models of Mainstream Reconfigurable Cryptographic Processing Architectures**
Currently, two primary types of reconfigurable cryptographic architectures exist: array-based (such as ADRES, XPP, and MorphoSys) and VLIW-based (like Cryptonite and CCproc). Among these, array-based architectures generally offer better performance in terms of data acceleration and resource utilization.
The ADRES architecture uses a very long instruction word processor, leading to a centralized control mode. While it supports periodic configuration updates, its highly customized nature results in large area and poor scalability. The XPP architecture, with a semi-centralized control approach, allows each processing cluster to generate at least one control flow, offering greater flexibility than ADRES. However, when dealing with complex interactions between data and control flows, it can lead to inefficient algorithm mapping and high interaction overhead. The MorphoSys architecture, by contrast, only supports a single control flow, limiting its ability to handle multiple algorithms efficiently and causing delays in control-computation interactions.
To address these shortcomings, the traditional three-layer control model was enhanced into a four-layer structure. A programmable controller was introduced between the configuration page layer and the reconfigurable array, enabling feedback-based configuration selection and improving control-flow interaction. Further improvements led to a control network design based on a network interconnection structure, where each processing unit is equipped with a programmable controller (PCE), allowing for dynamic configuration and reducing power consumption during page switching.
**2. Research on Control Methods of Symmetric Cryptography**
Designing an efficient programmable controller for coarse-grained cryptographic arrays requires understanding the unique control characteristics of symmetric algorithms. This section explores several key control methods:
**2.1 Data Stream Multiplexing Control**
Symmetric algorithms, whether block ciphers, stream ciphers, or hash functions, typically follow an iterative pattern. Each operation is repetitive, and intermediate data depends only on the next set of inputs. This regularity allows for efficient multiplexing of data streams.
**2.2 Unequal Length Data Path Control**
When handling packets or hash computations, different data paths may require varying operations. Two common approaches are either padding shorter paths to match longer ones or using register waiting to synchronize different streams. This paper proposes a register-based waiting mechanism that improves resource utilization and reduces control complexity.
**2.3 Switching Control**
Symmetric algorithms often consist of multiple stages, such as initial setup, round operations, and output generation. The control flow must dynamically switch between these stages. For example, block ciphers have distinct phases, while hash algorithms operate in a uniform manner across all rounds.
**2.4 Clock Control and Control Structure Control**
Clock control introduces uncertainty into sequence ciphers, requiring dynamic adjustments to the data flow map. One approach integrates control flow into the data stream, while another extracts clock-related bits and sends them to the control flow for decision-making. Both methods have trade-offs in terms of resource usage and complexity.
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