The CPCI bus is currently the popular high-speed embedded computer bus. At present, the interface of most embedded computer systems finally has to interact with the computer memory through the CPCI bus. The CPCI bus specification guarantees good compatibility and reliability.
The system designed in this paper adopts the PCIC4 protocol conversion chip PCI9054 produced by PLX Company, and generates corresponding control signals in the FPGA through Verilog HDL language to complete the fast reading and writing of data, thus realizing high-speed data communication with CPCI bus.
1 system design
The system is mainly composed of PCI9054 and FPGA. The system structure diagram and signal connection are shown in Figure 1. By utilizing the programmability of the FPGA, more extended functions can be realized, such as indirect high-speed communication with different speeds such as DSP and A/D. The role of the protocol conversion chip PCI9054 is to ensure that the data between the local data acquisition board and the main CPU board can be transmitted at high speed and accuracy.
2 PCI9054 performance analysis
PCI9054 is a general-purpose interface chip based on the PCI V2.2 bus specification produced by PLX. It supports both single-byte and burst mode transmission methods. The bus terminal supports 32-bit/33 MHz transmission, and the local end can achieve a maximum transmission rate of 132 Mbit·s-1 in burst mode, and can control the bus width of the local end.
PCI9054 can be seen as a bridge between the CPCI bus and the local user local bus. Because the PCI9054 has six programmable FIFO memories for data buffering, it ensures the correctness and real-time performance of data transmission between the two. And PCI9054 allows either end to act as the master device to control the bus, while the other end acts as the target device to respond to the bus.
The PCI9054 has multiple register banks inside to control the working state and working mode of its two ends. PCI9054 has a uniform address mapping for all its internal register banks and FIFOs. Users can programmatically access all the FIFOs and register bytes from both ends to view the working status of both ends and change the working mode of both ends.
3 PCI9054 local bus interface design
The design idea of ​​the entire CPCI interface is: FPGA connects to the CPCI bus through the bridge chip PCI9054, and internally uses asynchronous dual-port RAM to buffer high-speed data, and uses VerilogHDL language programming to control the asynchronous dual-port RAM in the FPGA to realize the system. The data is transmitted at high speed between the embedded CUP board memory and the CPCI board.
PCI9054 provides three physical bus interfaces: CPCI bus interface, LOCAL bus interface and serial EPROM interface. The driver package of the CPCI bus interface protocol in the embedded operating system is already included, and the initialization of the serial EEPROM is written by the PLXMON software of the PLX company in the embedded operating system, so the focus of the system design is Regarding the control and transmission of the LOCAL bus interface, the interface circuit diagram is shown in Figure 2.
The interface between the PCI9054 and the local bus is called LOCAL BUS, which is a very important part of the CPCI bus system design. PCI9054 LOCAL BUS In the system design, the bus is directly connected to the data bus of Alter's EP2S90F78014 chip, and the function of the dual-port RAM controller is realized by using Verilog HDL language programming.
The PCI9054 LOCAL BUS has three operating modes, M, J, and C modes. The M mode was developed and designed specifically for Motorola, while the other two modes of operation are more widely used. The J mode does not have a LocaL Master, so its address bus and data lines are not separated, which increases the development difficulty. In the C mode, the PCI9054 chip can separate the local address of the CPCI and the data bus through on-chip logic control, thereby effectively reducing the development difficulty, and providing various working modes flexibly for the local working sequence, so the system The design chose the C mode of operation of the LOCAL bus and operates at 40 MHz.
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