OverviewDS31256 has 256 independent direcTIonal HDLC channels, which support up to 64 T1 or E1 data streams. Sixteen channelized or unchannelized ports and each channelized port can handle one, two, or four T1 or E1 lines. There are also three fast ports on DS31256, which can handle up to 52 Mbps in both transmit and receive direcTIons, suitable for HSSI or clear channel T3 applicaTIons. All sixteen ports can operate from zero to 10 Mbps when configured in unchannelized mode of operations. Types of T1 / E1 ApplicationsThere are two types of channelized T1 and E1 applications: The first type is where a single T1 or E1 data stream is routed to and from one of the sixteen physical ports of the DS31256. This first type is represented as a thin arrow (Figure 1) in the application examples and the electrical connections are shown in Figure 2. The second type is where four T1 or E1 data streams have been Time Division Multiplexed (TDM) into a single 8.192MHz data stream, which is routed to and from the DS31256. This second type is represented as a thick arrow in Figure 1 and the electrical connections are shown in Figure 3.
Figure 1. Application drawing key.
Figure 2. Single T1 / E1 connection.
Figure 3. Quad T1 / E1 connection.
An application shows where 16 T1 or E1 links are framed and interfaced to a single DS31256. The T1 lines can be either clear-channel or channelized. The DS26528 Octal T1 / E1 / J1 single-chip transceiver performs the line interface function and frames to the T1 / E1 / J1 line.
Figure 4. 16 Port T1 application.
An application shows where two T3 lines are interfaced to a single DS31256. The T3 lines are demultiplexed by DS3112 M13 devices and passed to the DS21FF42 4 x 4 16-channel T1 framer and DS21FT42 4 x 3 12-channel T1 framer devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256 by aggregating four T1 lines into a single 8.192MHz data stream, which then flows into and out of the DS31256. The T1 lines can be either clear channel or channelized.
Figure 5. Dual T3 with 256 HDLC channel support.
An application shows where a T3 line is interfaced to two DS31256s. The T3 line is demultiplexed by the M13 block and passed to the DS21FF42 and DS21FT42 devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256. Aggregating four T1 lines into a single 8.192MHz data stream is not required since the DS31256 has enough physical ports to support the application, but aggregation could be done to cut down on the number of electrical connections between the DS31256 and the T1 framers. The T1 lines can be either clear channel or channelized.
Figure 6. Single T3 with 512 HDLC channel support.
An application shows where a fully channelized T3 line is interfaced to three DS31256's. The T3 line is demultiplexed by the M13 block and passed to the DS21FF42 and DS21FT42 devices. The T1 framers locate the frame and multiframe boundaries and interface to the DS31256. Aggregating four T1 lines into a single 8.192MHz data stream is not required since the DS31256 has enough physical ports to support the application, but aggregation could be done to cut down on the number of electrical connections between the DS31256 and the T1 framers. The T1 lines can be either clear channel or channelized.
Figure 7. Single T3 with 672 HDLC channel support.
If you have further questions about our HDLC controller products, please contact the Telecommunication Applications support team via email var name = "telecom.support @"; var domain = "dalsemi.com"; document.write ("" + name + domain + ""); telecom. or call 972-371-6555.
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