Microcontrollers are widely used in the automotive and consumer markets, and can achieve high system integration at a relatively low cost. However, these products also have potential cost issues. For example, if the component function does not meet the requirements, it must be expanded using external logic, software, or other integrated devices. Moreover, with the rapid changes in the final market demand, microcontrollers will soon become obsolete. Many special function microcontrollers with a certain number of dedicated interfaces cannot fully meet market demand after short-term trials. Therefore, system vendors have to redesign the hardware and software, and even modify the processor core in some cases.
The dilemma faced by ASSP microcontrollers
Traditional microcontroller manufacturers face a dilemma that affects the entire market. Microcontrollers are special products, so for each application, new and different features must be used. In order to be able to respond to the broader market with a microcontroller core structure, manufacturers provide a series of microcontrollers with different model interfaces and functions. In many cases, these hybrid features cannot fully meet user needs. Therefore, in order to expand the customer base, new interfaces and functions must be developed around specific core structures.
This strategy was very successful when using older technology to implement microcontrollers at a lower production cost. However, the latest process technology is now used to improve system integration, so that the cost of developing new microcontrollers has greatly increased. Only a few customers have a large output demand, which shows that it is not a viable business practice to produce such special devices for one customer. For this reason, new microcontrollers tend to be standard products rather than dedicated devices, attracting the entire market with more and more functions. Although these additional features make microcontrollers more powerful, they also greatly increase costs, making them more difficult to apply to cost-sensitive markets such as the automotive and consumer industries. It is difficult to solve this problem without focusing on the chip function fundamentally.
Flexible microcontroller solutions
One of the solutions to this problem is to use FPGA to flexibly implement chip functions. These devices greatly shorten the engineering development time and reduce the cost of chip trial production, and are a powerful alternative to microcontrollers. In the design process, FPGA does not miss certain features like a microcontroller. It can be programmed and rewritten as needed to quickly complete prototype development and bring products to market more quickly. If the requirements change, even if the device has been applied to the product, it can be updated in the field.
The application of image controllers in automotive systems is an example where FPGAs are superior to traditional controllers. Although the automotive market requires low-cost FPGAs to implement various functions such as images, it requires a large number of chips. Therefore, the cost of implementing complex functions in programmable devices is too high.
The flexible microcontroller is not only cost-effective, but also very user-friendly. The reason why the price / performance ratio is good is because it uses a 90nm structured ASIC, such as Altera HardCopy device as the basic chip. Its functions are selected from a large number of predefined and flexible building block libraries, which can be customized according to customer needs. In the development process, the HardCopy structured ASIC is different from the traditional microcontroller, it supports seamless migration from the prototype FPGA to the microcontroller. The CPU and bus architecture are unique to the flexible microcontroller solution, and can be mapped to the design with appropriate functions and features for specific customer applications. The advantages of the HardCopy series include:
chip
* 50% faster than FPGA
* Core power consumption is 70% lower than FPGA
* 60% to 85% smaller die software * Unified FPGA and HardCopy design environment
* Power and performance management tools
* Low price, easy to use package
* Compatible with FPGA pins to pins
* Low-cost product packaging
* No need to remake the circuit board
RISC CPU
The CPU used in this solution is the Altera Nios II embedded processor. Unlike the general situation, it is not fixed in the predetermined chip, but uses actual tools to automatically generate according to the requirements of the system architecture, and the entire circuit The other logic required is loaded into the FPGA together. In this way, you can use Altera's SOPC Builder tool to parameterize the processor core according to the specific application to occupy the least logic and achieve the most suitable function.
N ios II processor adopts standard RISC architecture, with separate address bus and data bus, both of which are 32 bits wide. The two buses work through separate buffers and can be further separated in the bus system. Finally, it is up to the system designer to determine whether code and data use different memories or are placed in shared memory. The Nios II processor contains most of the functional units of each processor, and its settings determine its characteristics. For example, hardware multipliers, barrel shift registers, and hardware dividers can be selected according to requirements. The same is true for instruction and data buffers, and their capacity can be adjusted or not used at all.
Bus architecture
Traditionally, microcontrollers have always used a single bus, and the arbiter monitors the bus and allocates resources. This is very unfavorable to the bus. As the central resource of the system, it quickly becomes a bottleneck. Therefore, newer systems use a multi-layer bus, especially SoCs where multiple buses work in parallel. The working principle of Altera's Avalon bus structure is similar, the difference is that in other multi-layer buses, the number of layers is fixed, and Avalon can freely choose the number of layers required.
Taking into account EMC and power consumption issues, sometimes peripheral modules with different operating speeds from other parts of the system can be used. When the memory interface is running at a higher rate, the access time is relatively short, and the rest of the system is running at a lower clock rate, this method is more suitable. Many low-clock rate modules can also be integrated together. To meet EMC or power consumption requirements, using SOPC Builder can easily separate these units from other high-speed systems. This can automatically generate the logic required to synchronize different clock domains, and the designer only needs to specify which modules run on a given clock domain.
Figure 1 Automotive infotainment platform
Implement microcontroller in FPGA
Since this type of system is much more complicated than a simple image controller, in most cases,
FPGA is used as a prototype development tool. Using FPGA as a prototype greatly reduces the development risk, it can carry out comprehensive verification, firmware development and field testing.
Prototyping with FPGAs means that engineers can run devices in the system and test in real environments. In this way, engineers can identify potential design flaws that are difficult to find during simulation.
Software development is already a major part of the entire development cycle. Software development requires a lot of time and resources. Therefore, the prototype system can reduce the entire development cycle and find defects and compatibility issues.
On-site testing of the system is conducive to the discovery of system and device defects, which is difficult to achieve in the laboratory. In many cases, it is necessary for the sales staff to demonstrate the system in order to obtain the order. For the initial specification, some new features and functions need to be added. Regardless of the previously undiscovered problems or newly added features, FPGA prototype development can be quickly modified to reduce the large one-time engineering cost and shorten the production cycle. 
Figure 2 Flexible automotive microcontroller solution
The final unit in the flexible microcontroller solution is ASIC development. After the prototype system was built and tested, the design was handed over to Altera and converted to a HardCopy structured ASIC. Unlike other structured ASICs, HardCopy devices use the same building blocks as FPGA prototypes, so there is no need to re-synthesize the design or perform more verification. With a short turnaround time for HardCopy devices, designers can quickly complete FPGA logic and reduce costs as much as possible.
in conclusion
Next-generation automotive electronic systems need to use very professional low-cost devices to meet market demand. Taking into account the current rising cost of process technology development, the use of traditional microcontrollers is somewhat impractical, and multi-function devices aimed at a larger market are expensive and unsuitable. On the contrary, the flexible microcontroller solution develops suitable microcontrollers for specific applications and implements prototype development in FPGA. After the design is completed, verification, software development and field testing can be carried out immediately even during the design process. For mass production, FPGA designs are directly mapped to HardCopy structured ASICs without re-synthesis or verification.
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