A module is a basic descriptive unit of Verilog that describes the function or structure of a design and its external ports that communicate with other modules. A design structure can be described using switch-level primitives, gate-level primitives, and user-defined primitives; data is designed to be described using continuous assignment statements; time-series behavior is described using process structures. One module can be used in another module.
The basic syntax of a module is as follows:
Module module_name (port_list);
DeclaraTIons:
Reg, wire, parameter,
Input, output, inout,
funcTIon, task, . . .
Statements:
IniTIal statement
Always statement
Module instanTIation
Gate instantiation
UDP instantiation
Continuous assignment
Endmodule
The description section is used to define different items, such as the registers and parameters used in the module description. The statement defines the function and structure of the design. Description sections and statements can be scattered anywhere in the module; however, the descriptions of variables, registers, nets, and parameters must appear before use. In order to make the module description clear and well readable, it is best to put all the descriptions before the statement. All examples in this book follow this specification.
The following is a simple example of a module that models a half-adder circuit.
Module HalfAdder (A, B, Sum, Carry);
Input A, B;
Output Sum, Carry;
Assign #2 Sum = A ^ B;
Assign #5 Carry = A & B;
Endmodule
The name of the module is HalfAdder. The module has 4 ports: two input ports A and B, and two output ports Sum and Carry. Since the number of bits in the port is not defined, all ports are 1 bit in size; at the same time, since there is no data type description for each port, these four ports are all wire network data types.
The module contains two consecutive assignment statements that describe the behavior of the half adder data. In this sense, the order in which these statements appear in the module is irrelevant, and these statements are concurrent. The order in which each statement is executed depends on the events that occur on variables A and B.
In the module, a design can be described in the following way:
1) data flow mode;
2) the way of behavior;
3) Structure;
4) A mixture of the above described modes.
The following sections describe these design descriptions by way of example. However, it is necessary to first briefly introduce the delay of Verilog HDL.
All delays in the Verilog HDL model are defined in terms of time units. The following is an example of a continuous assignment statement with a delay.
Assign #2 Sum = A ^ B;
#2 refers to 2 time units.
Use a compile directive to associate a time unit with a physical time. Such compiler directives need to be defined before the module description as follows:
` timescale 1ns /100ps
This statement states that the delay time unit is 1 ns and the time precision is 100 ps (time precision means that all delays must be limited to 0.1 ns). If the module in which this compiler directive is located contains the continuous assignment statement above, #2 stands for 2ns.
If there is no such compiler directive, the Verilog HDL simulator will specify a default time unit. The default time unit is not specified in the IEEE Verilog HDL standard.
Data Flow Description The most basic mechanism for modeling a design with data flow description is to use continuous assignment statements. In a continuous assignment statement, a value is assigned to a net variable. The syntax of a continuous assignment statement is:
Assign [delay] LHS_net = RHS_ expression;
Whenever the operand used by the right expression changes, the right expression is recalculated, and the value of the change after the specified delay is assigned to the net variable of the left expression. The delay defines the duration between the operand change of the right expression and the assignment to the left expression. If no delay value is defined, the default delay is 0.
The following example shows an example model for modeling a 2-4 decoder circuit using data stream description.
`timescale 1ns/ 1ns
Module Decoder2x4 (A, B, EN, Z);
Input A, B, EN;
Output [ 0 :3] Z;
Wire Abar, Bbar;
Assign #1 Abar = ~ A; / / statement 1.
Assign #1 Bbar = ~ B; / / statement 2.
Assign #2 Z[0] = ~ (Abar & Bbar & EN) ; / / statement 3.
Assign #2 Z[1] = ~ (Abar & B & EN) ; / / Statement 4.
Assign #2 Z[2] = ~ (A & Bbar & EN) ; / / statement 5.
Assign #2 Z[3] = ~ (A & B & EN) ; / / statement 6.
Endmodule
The first statement starting with the backquote " ` " is the compiler directive, and the compiler directive `timescale sets the unit of all delays in the module to 1 ns with a time precision of 1 ns. For example, in consecutive assignment statements, delay values ​​#1 and #2 correspond to delays of 1 ns and 2 ns, respectively.
The module Decoder2x4 has 3 input ports and 1 4-bit output port. The wire mesh type describes two wired variables Abar and Bbar (the wire type is one of the wire mesh types). In addition, the module contains six consecutive assignment statements.
Statements 3, 4, 5, and 6 are executed when EN changes at the 5th ns. This is because EN is the operand of the right expression in these consecutive assignment statements. Z[0] is assigned a new value of 0 at 7 ns. Statements 1, 5, and 6 are executed when A changes at the 15th ns. Execution statements 5 and 6 do not affect the values ​​of Z[0] and Z[1]. Executing statement 5 causes the Z[2] value to become zero at 17 ns. Executing statement 1 causes Abar to be reassigned at 16 ns. The change in Abar, in turn, causes the Z[0] value to become 1 at 18 ns.
Note how continuous assignment statements model the data's data popularity; this modeling approach is implicit rather than explicit. In addition, consecutive assignment statements are executed concurrently, which means that the order in which each statement is executed is independent of the order in which it appears in the description.
The behavioral features of the design are described using the following process statement structure:
1) initial statement: This statement is only executed once.
2) always statement: This statement is always executed cyclically, or it is repeated.
Only register type data can be assigned in both statements. The register type data remains unchanged until the new value is assigned. All initialization statements and always statements are executed concurrently at time zero.
The following example is an example of modeling a 1-bit full adder circuit with an always statement.
Module FA_Seq (A, B, Cin, Sum, Cout);
Input A, B, Cin;
Output Sum, Cout;
Reg Sum, Cout;
Reg T1, T2, T3;
Always
@ ( A or B or Cin ) begin
Sum = (A ^ B) ^ Cin;
T1 = A & Cin;
T2 = B & Cin;
T3 = A & B;
Cout = (T1| T2) | T3;
End
Endmodule
The module FA_Seq has three inputs and two outputs. Since Sum, Cout, T1, T2, and T3 are assigned values ​​in the always statement, they are declared as reg types (reg is a type of register data type). There is an event control in the always statement (an expression immediately following the character @). Associated sequential procedures (begin-end pairs). This means that as long as an event occurs on A, B, or Cin, that is, the value of one of A, B, or Cin changes, the sequential process is executed. Statements in the sequential process are executed sequentially and are suspended after the execution of the sequential process ends. After the sequential process is completed, the always statement waits for events that occur on A, B, or Cin again.
The statements that appear in the sequence are examples of modular assignment of process assignments. The modular process assignment completes execution before the next statement is executed. Process assignments can have an optional delay.
The delay can be broken down into two types:
1) Inter-statement delay: This is the delay in the execution of the delay statement.
2) Intra-statement delay: This is the delay between the evaluation of the right-hand expression and the assignment of the left expression.
The following is an example of the delay between statements:
Sum = (A ^ B) ^ Cin;
#4 T1 = A & Cin;
The delay in the second statement specifies that the assignment is delayed by 4 time units. That is, wait for 4 time units after the first statement is executed, and then execute the second statement. The following is an example of a delay within a statement.
Sum = #3 (A^ B) ^ Cin;
The delay in this assignment means first calculating the value of the right expression, waiting for 3 time units, and then assigning it to Sum.
If no delay is defined in the process assignment, the default is 0 delay, that is, the assignment occurs immediately. This form, along with other forms of specifying statements in the always statement, is discussed in detail in Chapter 8.
The following is an example of an initial statement:
`timescale 1ns / 1ns
Module Test (Pop, Pid);
Output Pop, Pid;
Reg Pop, Pid;
Initial
Begin
Pop = 0; // statement 1.
Pid = 0; // statement 2.
Pop = #5 1; // statement 3.
Pid = #3 1; // Statement 4.
Pop = #6 0; // statement 5.
Pid = #2 0; // statement 6.
End
Endmodule
The initial statement contains a sequential procedure. This sequential process begins at 0 ns, and the initial statement hangs forever after all statements have been executed in the sequence. This sequential process contains an instance of a grouping process assignment with a delay within the defined statement. Statements 1 and 2 are executed at 0 ns. The third statement is also executed at time 0, causing the Pop to be assigned at the 5th ns. Statement 4 is executed at 5th ns and Pid is assigned at 8th ns. Similarly, Pop is assigned a value of 0 at 14 ns and Pid is assigned a value of 0 at 16 ns. After the sixth statement is executed, the initial statement is always suspended.
The structure can be described in Verilog HDL as follows:
1) Built-in door primitives (at the door level);
2) Switch level primitives (at the transistor level);
3) User-defined primitives (at the gate level);
4) Module instance (creating a hierarchy).
Connected to each other by using a wire net. The following structural description uses a full adder circuit example described by the built-in gate primitives.
Module FA_Str (A, B, Cin, Sum, Cout);
Input A, B, Cin;
Output Sum, Cout;
Wire S1, T1, T2, T3;
Xor
X1 (S1, A, B),
X2 (Sum, S1, Cin);
And
A1 (T3, A, B),
A2 (T2, B, Cin),
A3 (T1, A, Cin),
Or
O1 (Cout, T1, T2, T3);
Endmodule
In this example, the module contains the instance statement of the gate, that is, the instance statement containing the built-in gates xor, and and or. Gate instances are interconnected by wire network type variables S1, T1, T2, and T3. Since there is no specified order, the gate instance statements can appear in any order; the diagram shows a pure structure; xor, and and or are built-in gate primitives; X1, X2, A1, etc. are instance names. The list of signals immediately following each gate is its interconnection; the first in the list is the gate output and the rest is the input. For example, S1 is connected to the output of xor gate instance X1, while A and B are connected to the input of instance X1.
The 4-bit full adder can be described using four 1-bit full adder modules. The following is a structural description of the 4-bit full adder.
Module FourBitFA (FA, FB, FCin, FSum, FCout );
Parameter SIZE = 4;
Input [SIZE:1] FA, FB;
Output [SIZE:1] FSum
Input FCin;
Input FCout;
Wire [ 1: SIZE-1] FTemp;
FA_Str
FA1( .A (FA[1]), .B(FB[1]), .Cin(FCin),
.Sum(FSum[1]), .Cout(FTemp[2])),
FA2( .A (FA[2]), .B(FB[2]), .Cin(FTemp[1]),
.Sum(FSum[2]), .Cout(FTemp[2])),
FA3 (FA[3], FB[3], FTemp[2], FSum[3], FTemp[3],
FA4 (FA[4], FB[4], FTemp[3], FSum[4], FCout);
Endmodule
In this example, the module instance is used to model a 4-bit full adder. In a module instance statement, a port can be associated with a name or location. The first two instances, FA1 and FA2, use a naming association, that is, the name of the port and the wire network to which it is connected are explicitly described (each of which is of the form ".port_name (net_name)). The last two instance statements, The instances FA3 and FA4 associate the port with the wire network using location association. The order of association here is important. For example, in instance FA4, the first FA[4] is connected to port A of FA_Str, and the second FB[4] Connect to port B of FA_Str, and the rest is like this.
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