A lot of money and effort are spent on exploring the FinFET process. How long will it last and why should they be replaced?

In the near term, it is quite clear from the advanced chip technology roadmap. The chip is expected to be reduced to 10nm nodes based on today's FinFET process technology or another planar technology of the FD SOI process. But at 7nm and below, the current CMOS process roadmap is not very clear.

The semiconductor industry has explored some candidates for next-generation transistor technology. For example, at 7 nm, a high-mobility FinFET is used, and a group III-V element is used as a channel material to increase the charge mobility. Then, up to 5 nm, there may be two techniques, one of which is a permuted FET, and the other is a tunnel FET (TFET), which has a slight advantage in comparison. The reason is all because of static electricity problem of the final CMOS device, one kind is the structure that surrounds the grid around the channel. In contrast, TFETs rely on steep subthreshold slope transistors to reduce power consumption.

This contest is far from over. It is clear that the following consensus may have been reached among chip manufacturers: the structure choice of next-generation devices, including III-V FinFETs; FinFETs around the gate; quantum wells; silicon nanowires; SOI FinFETs and TFETs.

There is still a long way to go in the future. In addition, there is another way to use a vertical chip architecture, such as 2.5D/3D stacked chip and monolithic 3D IC.

In short, Intel, Taiwan Semiconductor Manufacturing Co., and some other companies, all believe that the ring-gap technology may prevail. Intel’s Mayberry said that Intel is also studying it, which may be a process roadmap that everyone can accept.

Chip manufacturers may need to develop more than one type of architecture because no single technology can be an ideal choice for future applications. Michael Mayberry, Intel’s vice president, director of component technology and manufacturing. This cannot be a single answer. There are many different answers that will target different market segments. ”

Intel also showed a strong interest in TFET technology, although others have different opinions. The ultimate winner and loser will depend on cost, manufacturability and functionality. Mayberry said that, for example, the most promising is that the gate of the transistor is surrounded by carbon nanowires, but we do not know how to implement it. So this may not be the best option. It must be capable of mass production.

Another issue is whether the industry can maintain the rhythm of the technology node that is still every two years. As more and more economic factors begin to play a role, it is believed that the time for the semiconductor industry to move to next-generation process nodes will slow down, and may even shrink by 70% instead of extending the next generation of process nodes.

Extended FinFET process

In 2014, Intel is expected to introduce second generation FinFET technology based on 14nm process. Also this year, Globe, TSMC and Samsung have plans to launch their 14nm-class first-generation FinFET technology.

Intel is also developing 10nm FinFET technology, but the question now is how does the industry extend the FinFET process? For FinFET technology, An Steegen, senior vice president of process technology at IMEC, said that the gate has lost control of the channel at 10 nm to 7 nm. Steegen said that the ideal solution is that we can minimize a single FinFET to a width of 5nm and a gate length of 10nm.

So at 7nm, the industry must consider a new technology choice. According to the roadmap of different products and the opinions of industry executives, the main approach is to use high mobility or III-V FinFET structures. Bradley Howard, vice president of the Etching Technology Division of Applied Materials, said that from the current situation, the III-V channel material may be inserted at the 7 nm node.

In today's silicon-based FinFET structures, electron mobility degrades at 7 nm. Due to the high electron transport capability of germanium (Ge) and III-V element materials, faster switching speeds are allowed. According to experts, the first III-V FinFET structure may consist of Ge in the pFET. Then, the next-generation III-V FinFET may consist of pFET or indium gallium arsenide (InGaAs) to form an NFET.

High-mobility FinFETs also face some challenges, including the need to integrate different materials and structures. To help solve some of the problems, the industry is developing a replacement process for silicon fins. It depends on your goal, but the III-V FinFET will be the most likely alternative to finning, Howard said. Basically what you do is replace the fins. You need to surround the silicon fins with oxides. This basically replaces silicon with Group III-V elements.