The flip-flop is a memory storage device with two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits, and is also an important unit circuit in digital logic circuits.
It has a wide range of applications in digital systems and computers. The flip-flop has two stable states, namely "0" and "1", which can be flipped from one stable state to another under the action of a certain external signal.
The flip-flop has a trigger composed of an integrated flip-flop and a gate. There are two types of trigger modes: level trigger and edge trigger.
The D flip-flop flips at the leading edge of the clock pulse CP (positive transition 0→1), and the state of the flip-flop depends on the state of the D-end before the rising edge of the pulse of the CP, that is, the second state = D. Therefore, it has two functions of setting 0 and setting 1. Due to
The circuit has a blocking function during CP=1, so during CP=1, the data state of the D terminal changes without affecting the output state of the flip-flop.
D flip-flops are widely used and can be used for digital signal registration, shift registering, frequency division and waveform generators.
D trigger principle learning guide:
Through the learning of this knowledge point, understand the working principle of the basic D flip-flop, master the truth function table, state transition truth table, characteristic equation and state transition diagram to describe the logic function of D flip-flop and the application of D flip-flop.
D trigger logic function
The sustain-block D flip-flop is triggered on the rising edge of the clock pulse CP, Figure 4-7(a) is its logic circuit, Figure 4-7(b) is the logical symbol, and the small rectangle of D in the logical symbol represents “ With the "gate, in order to expand the function of the trigger, often make multiple D inputs, D = D1D2....
What is the use of d triggers?The master-slave JK flip-flop receives the signal during the high period of the CP pulse. If an interference signal appears at the input during the CP high level, it is possible to cause the flip-flop to generate an error condition that does not match the logic function table. The circuit structure of the edge trigger enables the trigger to receive the signal immediately before the effective trigger edge of the CP pulse, and the state transition occurs after the effective trigger edge arrives. The trigger of the circuit structure greatly improves the anti-interference ability and the circuit operation. reliability. The following describes the working principle of the edge trigger by taking the maintenance of the blocking D flip-flop as an example.
The logic diagram and logical symbols for maintaining a blocking edge D flip-flop are shown in Figure 9-7. The flip-flop is composed of six NAND gates, wherein G1 and G2 form a basic RS flip-flop, G3 and G4 form a clock control circuit, and G5 and G6 constitute a data input circuit. with
They are directly set to 0 and directly set to 1 and the active level is low. When analyzing the working principle, set the sum to be high level, which does not affect the work of the circuit. The circuit works as follows.
3 After the trigger is flipped, the input signal is blocked when CP=1. After G3 and G4 are turned on, their output and
The state is complementary, that is, there must be one, if
0, the G6 is output to the feedback line of the G6 input to block G6.
That is, the path of D to the basic RS flip-flop is blocked; the feedback line serves to maintain the flip-flop in the 0 state and prevent the flip-flop from becoming the 1 state, so the feedback line is called the 0-maintaining line, and the blocking line is set to block. line. When G3 is 0, G4 and G5 are blocked, and the path from the D terminal to the basic RS flip-flop is also blocked; the G3 output terminal to the G5 feedback line serves to maintain the flip-flop in the 1 state, which is called the set-one maintenance line. The feedback line from the G3 output to the G4 input acts to prevent the trigger from being set to 0, which is called the 0 blocked line. Therefore, this trigger is called a hold blocking trigger.
It can be seen from the above analysis that the sustaining blocking D flip-flop generates a state change on the rising edge of the CP pulse, the secondary state of the flip-flop depends on the signal of the D-end before the rising edge of the CP pulse, and after the rising edge, the signal of the input D-end changes to the flip-flop. The output state has no effect. If the rising edge of the CP pulse comes before 0, the flip-flop is set to 0 after the rising edge of the CP pulse; if the rising edge of the CP pulse comes before = 1, the flip-flop is after the rising edge of the CP pulse. Set to 1. The logical function table for maintaining the blocking trigger is shown in Table 9-4.
Solution: The D flip-flop is a rising edge trigger, that is, after the rising edge of the CP, the state of the flip-flop is equal to the state of D before the rising edge of the CP pulse. So after the first CP, =1, after the second CP, = 0, ..., the waveform is shown in Figure 9-8. The flip-flop accepts the input signal before the rising edge of the CP, and the rising edge triggers the flip, that is, the output state change of the flip-flop is delayed than the state change of the input end, which is the origin of the flip-flop.
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