A microcontroller is a single-chip microcomputer that integrates the main part of a microcomputer on a single chip. Microcontrollers were born in the mid-1970s. After more than 20 years of development, their cost is getting lower and lower, and their performance is getting stronger and stronger, which makes their applications ubiquitous in all fields. Examples include motor control, bar code readers/scanners, consumer electronics, gaming equipment, telephones, HVAC, building security and access control, industrial control and automation, and white goods (washing machines, microwave ovens).
classification
Microcontrollers (MCUs) can be classified from different aspects: according to the data bus width can be divided into 8-bit, 16-bit and 32-bit machines; according to the memory structure can be divided into Harvard structure and VonNeumann structure; according to embedded program memory The categories can be divided into OTP, mask, EPROM/EEPROM and flash memory; according to the instruction structure, it can be divided into CISC (ComplexInstructionSetComputer) and RISC (ReducedInstructionSetComputer) microcontrollers.
development path
Intel, the first company to introduce a microprocessor, was also the first company to introduce a microcontroller. Following the introduction of the MCS-48 in 1976, the MCS-51 was introduced in 1980, laying a good foundation for the development of a new generation of microcontrollers with good compatibility. After the 8051 technology was implemented, companies such as Philips, Atmel, Dallas, and Siemens introduced microcontrollers based on the 80C5l core (805l CMC) S version. These unique products meet the needs of a large number of embedded applications. Microcontrollers based on the 80C51 core have not stopped developing. For example, the DS89C430 series of microcontrollers from Maxim/Dallas now have a single-cycle instruction speed that has been increased to 12 times that of the 805l.
In addition to the 80C51, the CISC-based microcontroller also includes the 68HC series of microcontrollers from Motorola, which is also a series of 8-bit microcontrollers for a large number of applications.
RISC-based microcontrollers include Microchip's PIC family of 8-bit microcontrollers. Among the 16-bit RISC-based microcontrollers, Maxim's MAXQ family of microcontrollers has become a high-performance mixed-signal processing and portable system and battery-powered system with high performance, low power consumption and excellent code execution efficiency. The ideal choice.
Kernel based on 8051 core CISC microcontroller
To date, the MCS-51 has become the slowest running series of 8-bit machines. Now Dallas' DS89C430 series products are compatible with the 80C51 pin and instruction set, with only one clock per machine cycle, achieving the highest throughput of the 8051 series. In general, the existing 8051-based application software can be written directly to the DS89C430 without modification. In addition, the DS89C430 introduces new features in many other areas to provide more flexibility for specific applications. The following describes the features and features of the DS89C430 different from the 8051.
On-chip program memory and application
On-chip program memory is logically divided into pairs of 8KB, 16KB or 32KB flash cells to support in-application programming. This allows the device to modify the program memory under the control of the application software, and the application system can perform online software upgrades while performing its main functions. The DS89C430 integrates a 64B encryption array that allows users to view data in encrypted form for program code verification.
The device supports in-system programming via the RS-232 serial port. System booting activates the bootloader by setting one or more external pins of the device to a particular state. After the device boots up, it begins executing the loader that resides in the device's internal dedicated ROM. Once a carriage return is received, the serial port performs an auto-baud function and synchronizes with the host's baud rate. Figure 1 shows the physical connection in the system programming. A simple bootloader interface allows several methods to be used to implement PC and target micro-control
Communication between devices. The easiest way is to use the Dallas Microcontroller Toolkit (MTK) software. It features a high-end front-end feature that simplifies task configuration such as target configuration, uploading, downloading code, and special feature configurations.
Double data pointer
The 8051 microcontroller accesses the off-chip data space via the MOVX instruction, and the entire 64KB off-chip data memory is accessed using the MOVX@DPTR instruction. The traditional 8051 has only one data pointer DPTR, and it is very troublesome to move data from one address to another. The DS89C430 has dual data pointers DPTR0 and DPTR1, so the software can use one pointer to load the source address and another to load the destination address. The SFR address of DPTR0 is the same as that of the 8051 (82H and 83H), so the source code does not need to be changed when using this pointer, and DPTR1 is located at the 84H and 85H addresses. All operations related to the data pointer use the active data pointer, which is selected by the control bit SEL. Each pointer also has its own
A control bit that determines whether the INCDPTR operation increments or decrements the data pointer value.
When copying a block of data, double data pointers can save a lot of code compared to using a single data pointer. The user converts the active data pointer by converting the SEL bit, one of which can be implemented by executing the INCDPS instruction. For these large block copies, the user must frequently execute this instruction to convert DPTR0 and DPTR1. In order to save speed and efficiency while saving code, the DS89C430 includes a conversion select bit (TSL) to determine whether the hardware automatically converts the SEL bit when executing the MOVX instruction. This eliminates the INCDPS instruction and further increases the speed.
Large block copies require the source and destination pointers to address the data space byte by byte. The traditional approach is to increase the data pointer by using the INCDPTR instruction. To further increase the data transfer rate, an automatic increase and decrease control bit (AID) is introduced to determine whether the active pointer value is automatically incremented or decremented when the MOVX instruction is executed. Table 1 shows the speed comparison of the DS80C320 and DS89C430 for 64B data block transmission under various conditions. As can be seen from Table 1, the running speed is greatly improved after using the double data pointer.
Power management and clock division control
The power consumption of a CMOS circuit is mainly composed of two parts: the static power consumption caused by continuous leakage current and the dynamic power consumption caused by the switching switch current required to charge and discharge the load capacitance. Among them, dynamic power consumption is the main part of the overall power consumption, which can be calculated by load capacitance (CL), power supply voltage (VDD) and operating frequency (f), namely: PD=CL×VDD2×f .
For a specific application, the capacitance and power supply voltage are relatively fixed, and the processing speed of the processor may be different at different times. Therefore, the operating frequency can be adjusted according to different needs, thereby achieving power consumption reduction without affecting system performance. Claim.
The DS89C430 supports three low power modes.
1 system clock divider control: allows the microcontroller to continue working with the internal fractional clock source to save power. The clock division control bit is set by software, and the working rate is set to 1024 oscillator cycles per machine cycle.
2 Idle mode: keeps the program counter statically and suspends the processor. In this mode, the processor does not fetch instructions or execute instructions. All resources are saved except that the peripheral interface clock remains active and the timer, watchdog, serial, and power monitoring functions are still working. The processor can exit the idle mode using the allowed interrupt source.
3 shutdown mode: disable all circuits inside the processor. All on-chip clocks, timers, and serial communications are stopped and the processor does not execute any instructions. The processor is able to exit the shutdown mode by using any of the six external interrupts.
Architecture based RISC architecture microcontroller
The MAXQ2000 microcontroller is a RISC-based 16-bit microcontroller from Maxino/Dallas. Understanding some of the structural features of this microcontroller will allow us to better understand the latest trends and technical features of RISC-structured microcontrollers, thus providing us with a better choice for building new systems. The MAXQ2000 instruction read and execute operations are completed in one cycle without pipeline operation because the instructions contain both opcodes and data. The letter Q indicates that an important feature of this microcontroller is "quiet", and the MAXQ architecture reduces noise by intelligent clock management. This means that MAXQ only clocks those circuits that need to use the clock, which reduces power consumption and provides the quietest environment for analog circuit integration. It includes a liquid crystal display (LCD) interface that can drive up to 100 or 132 segments (both versions). The microcontroller's power consumption and MIPS/MHz code efficiency are among the best in its class. The main features of the MAXQ2000 are described below.
Instruction Set
The instruction set consists of 23 fixed-length 16-bit instructions that operate on registers and memory. The instruction set is highly orthogonal, allowing arithmetic and logic operations to use the accumulator and any registers. The special function registers control the peripherals and are subdivided into register modules. The structure of the product line is modular, so new devices and modules can continue to use code developed for existing products. This structure is based on transfer triggering, which means that reading or writing to a register location has an additional effect. These additional effects form the basis of high-level opcodes defined by the assembler, such as ADDC, OR, and JUMP.
Memory
The MAXQ2000 has 32KB of flash memory, 1KB of RAM, 4KB of internal ROM memory blocks, and 16 levels of stack memory. The memory is configured by default into a Harvard structure. The program and data memory have separate address spaces. It can also enable the VorlNcumann memory configuration mode, which places the fixed-purpose ROM, code, and data memory into a contiguous memory map. This is suitable for applications that require dynamic program modification or special memory configuration. The Flash program memory can be password protected with a 16-word key to prevent unauthorized access to the program memory. At the same time, it also has 3 data pointers to support efficient and fast processing of data.
The utility ROM consists of subroutines that can be called in the application software (the default starting address is 8000H). Including: in-system programming (bootloader) via JTAG or UART interface; in-circuit debugger; tester (internal memory test, memory load, etc.); user-callable program for application flash programming and fast lookup tables. Whether reset in any way, the program is run from the fixed-purpose ROM. R. The M software determines that the program immediately jumps to the 8000H location, the start of the user application code, or a specific use subroutine mentioned above. Users can access programs in the utility ROM and can be called by the application software.
Register bank
Most of the device's functionality is controlled by a register bank. These registers provide a workspace for memory operations and configure and address peripheral registers on the device. Registers fall into two broad categories: system registers and peripheral registers. Common register sets are also referred to as system registers, including ALUs, accumulator registers, data pointers, stack pointers, and so on. Peripheral registers define additional features that may be included in different products based on the MAXQ architecture.
Power management
The MAXQ2000 also provides advanced power management features that dynamically set processing speeds based on different performance requirements at different points in the system, resulting in significant power savings. The frequency division function is selected by software to select whether the system clock period is 1, 2, 4 or 8 vibrating cycles. To further reduce power consumption, there are three other low-power modes, 256-divided, 32kH. And shutdown mode.
Interrupt
Multiple interrupt sources are provided to respond quickly to internal and external events. The MAXQ architecture uses a single interrupt vector (IV) and a single interrupt service routine (ISR) design. The interrupt flag must be cleared within the user interrupt routine to avoid repeated interrupts caused by the same interrupt source. When an enabled interrupt is detected, the software jumps to a user-programmable interrupt vector location.
Once software control is transferred to the ISR, the Interrupt Identification Register (IIR) can be used to determine if the interrupt source is a system register or a peripheral register. Then, you can query a specific module to determine the specific source of the interrupt and take the appropriate action. Since the interrupt source is recognized by the user software, the user can establish a unique interrupt priority scheme for each application.
Hardware multiplier
The integrated hardware multiplier module performs high-speed multiply, power, and accumulate operations and can perform a 16-bit × 16-bit multiply and accumulate operation in one cycle. The hardware multiplier consists of two 6-bit parallel load operand registers (MA, MB) and one accumulator. The load register automatically initiates the operation, saving time in double counting. The accumulation function of the hardware multiplier is a basic unit in digital filtering, signal processing, and PII) control systems, which makes the MAXQ2000 suitable for applications that require a lot of mathematical operations.
Prospects
Through the above two based on CISC. A comparative analysis of microcontrollers with RISC architectures reveals many common features such as security features, peripherals, power management, and in-system programming. Obviously. They are all functions that are adapted to the common requirements of a particular application. The biggest difference between the two is the difference in instruction structure. MCS-5l has 50 basic instructions. If all kinds of different addressing modes are accumulated, the total number of instructions is lll. The corresponding machine instructions have single-byte, double-byte and three-byte instructions~68H(:05 has 62 basic instructions. With a variety of addressing methods, the final instruction reaches 210, which is also divided into single-byte, double-byte and three-byte instructions. In comparison, RIS (: all instructions of the microcontroller are made up of some simple, etc. The length of the instruction constitutes. The reduced instruction allows the microcontroller's line to be optimized as much as possible, and the hardware structure is simpler, so that lower cost and power consumption can be achieved. Of course, more instructions may be required to complete the same work. There is no absolute advantage between them. It can only be said that the choices are based on the different needs and priorities of the application.
Microprocessors are one of the great technological innovations of the 20th century. The resulting microcontrollers combine microprocessors and peripherals to create a new dimension for a variety of applications and will continue to play an irreplaceable role.
Architecture Harvard Architecture
The Harvard architecture is a memory structure that separates program instruction storage from data storage. The central processor first reads the program instruction content into the program instruction memory, obtains the data address after decoding, and then reads the data into the corresponding data memory, and performs the next operation (usually execution). Program instruction storage and data storage are separate, allowing instructions and data to have different data widths. For example, Microchip's PIC16 chip program instructions are 14 bits wide and the data is 8 bits wide.
Harvard-structured microprocessors typically have higher execution efficiency. The program instructions and data instructions are separately organized and stored, and the next instruction can be read in advance during execution. At present, there are many central processing units and microcontrollers using Harvard architecture. In addition to the above mentioned PIC series chips from Microchip, there are Motorola's MC68 series, Zilog's Z8 series, ATMEL's AVR series and the company. The ARM9, ARM10 and ARM11, 51 single-chip microcomputers also belong to the Harvard structure.
Neumann structure
The von Neumann structure, also known as the Princeton structure, is a memory structure that combines program instruction memory and data memory. The program instruction memory address and data memory address point to different physical locations of the same memory, so the program instructions and data have the same width. For example, Intel's 8086 central processor program instructions and data are 16 bits wide.
There are many central processors and microcontrollers currently using the von Neumann structure. In addition to the Intel Corporation's 8086 mentioned above, Intel's other central processors, ARM's ARM7, and MIPS' MIPS processors also use the von Neumann structure.
classification
Microcontrollers (MCUs) can be classified from different aspects: according to the data bus width can be divided into 8-bit, 16-bit and 32-bit machines; according to the memory structure can be divided into Harvard structure and VonNeumann structure; according to embedded program memory The categories can be divided into OTP, mask, EPROM/EEPROM and flash memory; according to the instruction structure, it can be divided into CISC (ComplexInstructionSetComputer) and RISC (ReducedInstructionSetComputer) microcontrollers.
development path
Intel, the first company to introduce a microprocessor, was also the first company to introduce a microcontroller. Following the introduction of the MCS-48 in 1976, the MCS-51 was introduced in 1980, laying a good foundation for the development of a new generation of microcontrollers with good compatibility. After the 8051 technology was implemented, companies such as Philips, Atmel, Dallas, and Siemens introduced microcontrollers based on the 80C5l core (805l CMC) S version. These unique products meet the needs of a large number of embedded applications. Microcontrollers based on the 80C51 core have not stopped developing. For example, the DS89C430 series of microcontrollers from Maxim/Dallas now have a single-cycle instruction speed that has been increased to 12 times that of the 805l.
In addition to the 80C51, the CISC-based microcontroller also includes the 68HC series of microcontrollers from Motorola, which is also a series of 8-bit microcontrollers for a large number of applications.
RISC-based microcontrollers include Microchip's PIC family of 8-bit microcontrollers. Among the 16-bit RISC-based microcontrollers, Maxim's MAXQ family of microcontrollers has become a high-performance mixed-signal processing and portable system and battery-powered system with high performance, low power consumption and excellent code execution efficiency. The ideal choice.
Kernel based on 8051 core CISC microcontroller
To date, the MCS-51 has become the slowest running series of 8-bit machines. Now Dallas' DS89C430 series products are compatible with the 80C51 pin and instruction set, with only one clock per machine cycle, achieving the highest throughput of the 8051 series. In general, the existing 8051-based application software can be written directly to the DS89C430 without modification. In addition, the DS89C430 introduces new features in many other areas to provide more flexibility for specific applications. The following describes the features and features of the DS89C430 different from the 8051.
On-chip program memory and application
On-chip program memory is logically divided into pairs of 8KB, 16KB or 32KB flash cells to support in-application programming. This allows the device to modify the program memory under the control of the application software, and the application system can perform online software upgrades while performing its main functions. The DS89C430 integrates a 64B encryption array that allows users to view data in encrypted form for program code verification.
The device supports in-system programming via the RS-232 serial port. System booting activates the bootloader by setting one or more external pins of the device to a particular state. After the device boots up, it begins executing the loader that resides in the device's internal dedicated ROM. Once a carriage return is received, the serial port performs an auto-baud function and synchronizes with the host's baud rate. Figure 1 shows the physical connection in the system programming. A simple bootloader interface allows several methods to be used to implement PC and target micro-control
Communication between devices. The easiest way is to use the Dallas Microcontroller Toolkit (MTK) software. It features a high-end front-end feature that simplifies task configuration such as target configuration, uploading, downloading code, and special feature configurations.
Double data pointer
The 8051 microcontroller accesses the off-chip data space via the MOVX instruction, and the entire 64KB off-chip data memory is accessed using the MOVX@DPTR instruction. The traditional 8051 has only one data pointer DPTR, and it is very troublesome to move data from one address to another. The DS89C430 has dual data pointers DPTR0 and DPTR1, so the software can use one pointer to load the source address and another to load the destination address. The SFR address of DPTR0 is the same as that of the 8051 (82H and 83H), so the source code does not need to be changed when using this pointer, and DPTR1 is located at the 84H and 85H addresses. All operations related to the data pointer use the active data pointer, which is selected by the control bit SEL. Each pointer also has its own
A control bit that determines whether the INCDPTR operation increments or decrements the data pointer value.
When copying a block of data, double data pointers can save a lot of code compared to using a single data pointer. The user converts the active data pointer by converting the SEL bit, one of which can be implemented by executing the INCDPS instruction. For these large block copies, the user must frequently execute this instruction to convert DPTR0 and DPTR1. In order to save speed and efficiency while saving code, the DS89C430 includes a conversion select bit (TSL) to determine whether the hardware automatically converts the SEL bit when executing the MOVX instruction. This eliminates the INCDPS instruction and further increases the speed.
Large block copies require the source and destination pointers to address the data space byte by byte. The traditional approach is to increase the data pointer by using the INCDPTR instruction. To further increase the data transfer rate, an automatic increase and decrease control bit (AID) is introduced to determine whether the active pointer value is automatically incremented or decremented when the MOVX instruction is executed. Table 1 shows the speed comparison of the DS80C320 and DS89C430 for 64B data block transmission under various conditions. As can be seen from Table 1, the running speed is greatly improved after using the double data pointer.
Power management and clock division control
The power consumption of a CMOS circuit is mainly composed of two parts: the static power consumption caused by continuous leakage current and the dynamic power consumption caused by the switching switch current required to charge and discharge the load capacitance. Among them, dynamic power consumption is the main part of the overall power consumption, which can be calculated by load capacitance (CL), power supply voltage (VDD) and operating frequency (f), namely: PD=CL×VDD2×f .
For a specific application, the capacitance and power supply voltage are relatively fixed, and the processing speed of the processor may be different at different times. Therefore, the operating frequency can be adjusted according to different needs, thereby achieving power consumption reduction without affecting system performance. Claim.
The DS89C430 supports three low power modes.
1 system clock divider control: allows the microcontroller to continue working with the internal fractional clock source to save power. The clock division control bit is set by software, and the working rate is set to 1024 oscillator cycles per machine cycle.
2 Idle mode: keeps the program counter statically and suspends the processor. In this mode, the processor does not fetch instructions or execute instructions. All resources are saved except that the peripheral interface clock remains active and the timer, watchdog, serial, and power monitoring functions are still working. The processor can exit the idle mode using the allowed interrupt source.
3 shutdown mode: disable all circuits inside the processor. All on-chip clocks, timers, and serial communications are stopped and the processor does not execute any instructions. The processor is able to exit the shutdown mode by using any of the six external interrupts.
Architecture based RISC architecture microcontroller
The MAXQ2000 microcontroller is a RISC-based 16-bit microcontroller from Maxino/Dallas. Understanding some of the structural features of this microcontroller will allow us to better understand the latest trends and technical features of RISC-structured microcontrollers, thus providing us with a better choice for building new systems. The MAXQ2000 instruction read and execute operations are completed in one cycle without pipeline operation because the instructions contain both opcodes and data. The letter Q indicates that an important feature of this microcontroller is "quiet", and the MAXQ architecture reduces noise by intelligent clock management. This means that MAXQ only clocks those circuits that need to use the clock, which reduces power consumption and provides the quietest environment for analog circuit integration. It includes a liquid crystal display (LCD) interface that can drive up to 100 or 132 segments (both versions). The microcontroller's power consumption and MIPS/MHz code efficiency are among the best in its class. The main features of the MAXQ2000 are described below.
Instruction Set
The instruction set consists of 23 fixed-length 16-bit instructions that operate on registers and memory. The instruction set is highly orthogonal, allowing arithmetic and logic operations to use the accumulator and any registers. The special function registers control the peripherals and are subdivided into register modules. The structure of the product line is modular, so new devices and modules can continue to use code developed for existing products. This structure is based on transfer triggering, which means that reading or writing to a register location has an additional effect. These additional effects form the basis of high-level opcodes defined by the assembler, such as ADDC, OR, and JUMP.
Memory
The MAXQ2000 has 32KB of flash memory, 1KB of RAM, 4KB of internal ROM memory blocks, and 16 levels of stack memory. The memory is configured by default into a Harvard structure. The program and data memory have separate address spaces. It can also enable the VorlNcumann memory configuration mode, which places the fixed-purpose ROM, code, and data memory into a contiguous memory map. This is suitable for applications that require dynamic program modification or special memory configuration. The Flash program memory can be password protected with a 16-word key to prevent unauthorized access to the program memory. At the same time, it also has 3 data pointers to support efficient and fast processing of data.
The utility ROM consists of subroutines that can be called in the application software (the default starting address is 8000H). Including: in-system programming (bootloader) via JTAG or UART interface; in-circuit debugger; tester (internal memory test, memory load, etc.); user-callable program for application flash programming and fast lookup tables. Whether reset in any way, the program is run from the fixed-purpose ROM. R. The M software determines that the program immediately jumps to the 8000H location, the start of the user application code, or a specific use subroutine mentioned above. Users can access programs in the utility ROM and can be called by the application software.
Register bank
Most of the device's functionality is controlled by a register bank. These registers provide a workspace for memory operations and configure and address peripheral registers on the device. Registers fall into two broad categories: system registers and peripheral registers. Common register sets are also referred to as system registers, including ALUs, accumulator registers, data pointers, stack pointers, and so on. Peripheral registers define additional features that may be included in different products based on the MAXQ architecture.
Power management
The MAXQ2000 also provides advanced power management features that dynamically set processing speeds based on different performance requirements at different points in the system, resulting in significant power savings. The frequency division function is selected by software to select whether the system clock period is 1, 2, 4 or 8 vibrating cycles. To further reduce power consumption, there are three other low-power modes, 256-divided, 32kH. And shutdown mode.
Interrupt
Multiple interrupt sources are provided to respond quickly to internal and external events. The MAXQ architecture uses a single interrupt vector (IV) and a single interrupt service routine (ISR) design. The interrupt flag must be cleared within the user interrupt routine to avoid repeated interrupts caused by the same interrupt source. When an enabled interrupt is detected, the software jumps to a user-programmable interrupt vector location.
Once software control is transferred to the ISR, the Interrupt Identification Register (IIR) can be used to determine if the interrupt source is a system register or a peripheral register. Then, you can query a specific module to determine the specific source of the interrupt and take the appropriate action. Since the interrupt source is recognized by the user software, the user can establish a unique interrupt priority scheme for each application.
Hardware multiplier
The integrated hardware multiplier module performs high-speed multiply, power, and accumulate operations and can perform a 16-bit × 16-bit multiply and accumulate operation in one cycle. The hardware multiplier consists of two 6-bit parallel load operand registers (MA, MB) and one accumulator. The load register automatically initiates the operation, saving time in double counting. The accumulation function of the hardware multiplier is a basic unit in digital filtering, signal processing, and PII) control systems, which makes the MAXQ2000 suitable for applications that require a lot of mathematical operations.
Prospects
Through the above two based on CISC. A comparative analysis of microcontrollers with RISC architectures reveals many common features such as security features, peripherals, power management, and in-system programming. Obviously. They are all functions that are adapted to the common requirements of a particular application. The biggest difference between the two is the difference in instruction structure. MCS-5l has 50 basic instructions. If all kinds of different addressing modes are accumulated, the total number of instructions is lll. The corresponding machine instructions have single-byte, double-byte and three-byte instructions~68H(:05 has 62 basic instructions. With a variety of addressing methods, the final instruction reaches 210, which is also divided into single-byte, double-byte and three-byte instructions. In comparison, RIS (: all instructions of the microcontroller are made up of some simple, etc. The length of the instruction constitutes. The reduced instruction allows the microcontroller's line to be optimized as much as possible, and the hardware structure is simpler, so that lower cost and power consumption can be achieved. Of course, more instructions may be required to complete the same work. There is no absolute advantage between them. It can only be said that the choices are based on the different needs and priorities of the application.
Microprocessors are one of the great technological innovations of the 20th century. The resulting microcontrollers combine microprocessors and peripherals to create a new dimension for a variety of applications and will continue to play an irreplaceable role.
Architecture Harvard Architecture
The Harvard architecture is a memory structure that separates program instruction storage from data storage. The central processor first reads the program instruction content into the program instruction memory, obtains the data address after decoding, and then reads the data into the corresponding data memory, and performs the next operation (usually execution). Program instruction storage and data storage are separate, allowing instructions and data to have different data widths. For example, Microchip's PIC16 chip program instructions are 14 bits wide and the data is 8 bits wide.
Harvard-structured microprocessors typically have higher execution efficiency. The program instructions and data instructions are separately organized and stored, and the next instruction can be read in advance during execution. At present, there are many central processing units and microcontrollers using Harvard architecture. In addition to the above mentioned PIC series chips from Microchip, there are Motorola's MC68 series, Zilog's Z8 series, ATMEL's AVR series and the company. The ARM9, ARM10 and ARM11, 51 single-chip microcomputers also belong to the Harvard structure.
Neumann structure
The von Neumann structure, also known as the Princeton structure, is a memory structure that combines program instruction memory and data memory. The program instruction memory address and data memory address point to different physical locations of the same memory, so the program instructions and data have the same width. For example, Intel's 8086 central processor program instructions and data are 16 bits wide.
There are many central processors and microcontrollers currently using the von Neumann structure. In addition to the Intel Corporation's 8086 mentioned above, Intel's other central processors, ARM's ARM7, and MIPS' MIPS processors also use the von Neumann structure.
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